Ethernet Subsystem Registers
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14.5.8.12 TS_LTYPE Register (offset = 2Ch) [reset = 0h]
TS_LTYPE is shown in Figure 14-195 and described in Table 14-212.
VLAN_LTYPE1 AND VLAN_LTYPE2 REGISTER
Figure 14-195. TS_LTYPE Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved TS_LTYPE2
R/W-0
15 14 13 12 11 10 9 8
TS_LTYPE1
R/W-0
7 6 5 4 3 2 1 0
TS_LTYPE1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-212. TS_LTYPE Register Field Descriptions
Bit Field Type Reset Description
21-16 TS_LTYPE2 R/W-0 0 Time Sync LTYPE2 This is an Ethertype value to match for tx and rx
time sync packets.
15-0 TS_LTYPE1 R/W-0 0 Time Sync LTYPE1 This is an ethertype value to match for tx and rx
time sync packets.
1436
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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