www.ti.com
Ethernet Subsystem Registers
14.5.6.51 P2_RX_DSCP_PRI_MAP6 Register (offset = 248h) [reset = 0h]
P2_RX_DSCP_PRI_MAP6 is shown in Figure 14-171 and described in Table 14-186.
CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6
Figure 14-171. P2_RX_DSCP_PRI_MAP6 Register
31 30 29 28 27 26 25 24
Reserved PRI55 Reserved PRI54
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved PRI53 Reserved PRI52
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved PRI51 Reserved PRI50
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI49 Reserved PRI48
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-186. P2_RX_DSCP_PRI_MAP6 Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI55 R/W 0h Priority
55 - A packet TOS of 0d55 is mapped to this received packet
priority.
26-24 PRI54 R/W 0h Priority
54 - A packet TOS of 0d54 is mapped to this received packet
priority.
22-20 PRI53 R/W 0h Priority
53 - A packet TOS of 0d53 is mapped to this received packet
priority.
18-16 PRI52 R/W 0h Priority
52 - A packet TOS of 0d52 is mapped to this received packet
priority.
14-12 PRI51 R/W 0h Priority
51 - A packet TOS of 0d51 is mapped to this received packet
priority.
10-8 PRI50 R/W 0h Priority
50 - A packet TOS of 0d50 is mapped to this received packet
priority.
6-4 PRI49 R/W 0h Priority
49 - A packet TOS of 0d49 is mapped to this received packet
priority.
2-0 PRI48 R/W 0h Priority
48 - A packet TOS of 0d48 is mapped to this received packet
priority.
1409
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated