Functional Description
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Example 11-2. Interrupt Servicing (continued)
NOTE: An event may occur during step 4 while the IPR/IPRH bits are read as 0 and the application is
still in the interrupt service routine. If this happens, a new interrupt is recorded in the device
interrupt controller and a new interrupt generates as soon as the application exits in the interrupt
service routine.
Example 11-3 is less rigorous, with less burden on the software in polling for set interrupt bits, but can
occasionally cause a race condition as mentioned above.
Example 11-3. Interrupt Servicing
If you want to leave any enabled and pending (possibly lower priority) interrupts; you must force the interrupt
logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register (IEVAL).
The pseudo code is as follows:
1. Enters ISR.
2. Reads IPR/IPRH.
3. For the condition that is set in IPR/IPRH that you want to service, do the following:
(a) Service interrupt as the application requires.
(b) Clear the bit for serviced conditions (others may still be set, and other transfers may have resulted in
returning the TCC to EDMA3CC after step 2).
4. Reads IPR/IPRH prior to exiting the ISR:
(a) If IPR/IPRH is equal to 0, then exit the ISR.
(b) If IPR/IPRH is not equal to 0, then set IEVAL so that upon exit of ISR, a new interrupt triggers if any
enabled interrupts are still pending.
11.3.9.3 Interrupt Evaluation Operations
The EDMA3CC has interrupt evaluate registers (IEVAL) that exist in the global region and in each shadow
region. The registers in the shadow region are the only registers in the DMA channel shadow region
memory map that are not affected by the settings for the DMA region access enable registers
(DRAE/DRAEH). Writing a 1 to the EVAL bit in the registers that are associated with a particular shadow
region results in pulsing the associated region interrupt (global or shadow), if any enabled interrupt (via
IER/IERH) is still pending (IPR/IPRH). This register assures that the CPU does not miss the interrupts (or
the EDMA3 master associated with the shadow region) if the software architecture chooses not to use all
interrupts. See Example 11-3 for the use of IEVAL in the EDMA3 interrupt service routine (ISR).
Similarly an error evaluation register (EEVAL) exists in the global region. Writing a 1 to the EVAL bit in
EEVAL causes the pulsing of the error interrupt if any pending errors are in EMR/EMRH, QEMR, or
CCERR. See Section 11.3.9.4 for additional information regarding error interrupts.
NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the
IEVAL operated upon is from that particular shadow region memory map.
906
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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