256255253 254249 250 251 252
244... ... 245 246 247 248
... ...17 18 19 20 21
12109 11 13 14 15 16
431 2 765 8Channel Source
Address (SRC)
244
252250249
...
251
... 245 246 247
253 254 255
248
256
Channel Destination
Address (DST)
12
20
11109
17 18 19
21 3
151413
21 ... ...
54 76
16
8
Functional Description
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11.3.19 EDMA Transfer Examples
The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration.
The following sections provide a description and PaRAM configuration for some typical use case
scenarios.
11.3.19.1 Block Move Example
The most basic transfer performed by the EDMA3 is a block move. During device operation it is often
necessary to transfer a block of data from one location to another, usually between on-chip and off-chip
memory.
In this example, a section of data is to be copied from external memory to internal L2 SRAM as shown in
Figure 11-22. Figure 11-23 shows the parameters for this transfer.
The source address for the transfer is set to the start of the data block in external memory, and the
destination address is set to the start of the data block in L2. If the data block is less than 64K bytes, the
PaRAM configuration shown in Figure 11-23 holds true with the synchronization type set to A-
synchronized and indexes cleared to 0. If the amount of data is greater than 64K bytes, BCNT and the B-
indexes need to be set appropriately with the synchronization type set to AB-synchronized. The STATIC
bit in OPT is set to prevent linking.
This transfer example may also be set up using QDMA. For successive transfer submissions, of a similar
nature, the number of cycles used to submit the transfer are fewer depending on the number of changing
transfer parameters. You may program the QDMA trigger word to be the highest numbered offset in the
PaRAM set that undergoes change.
Figure 11-22. Block Move Example
Figure 11-23. Block Move Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents Parameter
0010 0008h Channel Options Parameter (OPT)
Channel Source Address (SRC) Channel Source Address (SRC)
0001h 0100h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT)
Channel Destination Address (DST) Channel Destination Address (DST)
0000h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX)
0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK)
0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX)
0000h 0001h Reserved Count for 3rd Dimension (CCNT)
920
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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Copyright © 2011–2013, Texas Instruments Incorporated
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