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Ethernet Subsystem Registers
14.5.8.13 DLR_LTYPE Register (offset = 30h) [reset = 80E1h]
DLR_LTYPE is shown in Figure 14-196 and described in Table 14-213.
DLR LTYPE REGISTER
Figure 14-196. DLR_LTYPE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DLR_LTYPE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-213. DLR_LTYPE Register Field Descriptions
Bit Field Type Reset Description
15-0 DLR_LTYPE R/W-0 0
DLR LTYPE
14.5.9 CPSW_WR Registers
Table 14-214 lists the memory-mapped registers for the CPSW_WR. All register offset addresses not
listed in Table 14-214 should be considered as reserved locations and the register contents should not be
modified.
Table 14-214. CPSW_WR REGISTERS
Offset Acronym Register Name Section
0h IDVER Section 14.5.9.1
4h SOFT_RESET Section 14.5.9.2
8h CONTROL Section 14.5.9.3
Ch INT_CONTROL Section 14.5.9.4
10h C0_RX_THRESH_EN Section 14.5.9.5
14h C0_RX_EN Section 14.5.9.6
18h C0_TX_EN Section 14.5.9.7
1Ch C0_MISC_EN Section 14.5.9.8
20h C1_RX_THRESH_EN Section 14.5.9.9
24h C1_RX_EN Section 14.5.9.10
28h C1_TX_EN Section 14.5.9.11
2Ch C1_MISC_EN Section 14.5.9.12
30h C2_RX_THRESH_EN Section 14.5.9.13
34h C2_RX_EN Section 14.5.9.14
38h C2_TX_EN Section 14.5.9.15
3Ch C2_MISC_EN Section 14.5.9.16
40h C0_RX_THRESH_STAT Section 14.5.9.17
44h C0_RX_STAT Section 14.5.9.18
48h C0_TX_STAT Section 14.5.9.19
4Ch C0_MISC_STAT Section 14.5.9.20
50h C1_RX_THRESH_STAT Section 14.5.9.21
54h C1_RX_STAT Section 14.5.9.22
58h C1_TX_STAT Section 14.5.9.23
5Ch C1_MISC_STAT Section 14.5.9.24
60h C2_RX_THRESH_STAT Section 14.5.9.25
64h C2_RX_STAT Section 14.5.9.26
68h C2_TX_STAT Section 14.5.9.27
6Ch C2_MISC_STAT Section 14.5.9.28
1437
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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