DMTimer
www.ti.com
20.1.5.6 IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
IRQENABLE_SET is shown in Figure 20-14 and described in Table 20-16.
Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding
_CLR register.
Figure 20-14. IRQENABLE_SET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_EN_FLAG OVF_EN_FLAG MAT_EN_FLAG
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-16. IRQENABLE_SET Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 TCAR_EN_FLAG R/W 0h
IRQ enable for Capture
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Set IRQ enable
0x0x1(R) = IRQ event is enabled
1 OVF_EN_FLAG R/W 0h
IRQ enable for Overflow
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Set IRQ enable
0x0x1(R) = IRQ event is enabled
0 MAT_EN_FLAG R/W 0h
IRQ enable for Match
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Set IRQ enable
0x0x1(R) = IRQ event is enabled
3572
Timers SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
