Ethernet Subsystem Registers
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14.5.9.30 C0_TX_IMAX Register (offset = 74h) [reset = 0h]
C0_TX_IMAX is shown in Figure 14-226 and described in Table 14-244.
SUBSYSTEM CORE 0 TRANSMIT INTERRUPTS PER MILLISECOND
Figure 14-226. C0_TX_IMAX Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved C0_TX_IMAX
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-244. C0_TX_IMAX Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-0 C0_TX_IMAX R/W 0h Core 0 Transmit Interrupts per Millisecond - The maximum number
of interrupts per millisecond generated on C0_TX_PULSE if pacing
is enabled for this interrupt.
1468
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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