3GMAC
Switch Subsystem
L4 Fast
Interconnect
GMAC Switch
Pads
MPU
Subsystem,
PRU-ICSS
Interrupts
C1_INTS
GMII1_RXCLK
PRCM
L3 Fast
Interconnect
GMII1_RXD[3:0]
GMII1_RXDV
CPSW_3G
tx vbusp
rx vbusp
SCR
S
CPPI DMA
SLV
Int
M
C0_INTS
C2_INTs
Device
MDIO
Mstr
S
S
GMII1_RXER
GMII1_COL
GMII1_CRS
GMII1_TXD[3:0]
GMI I1_TXCLK
GMII1_TXEN
MDIO_MCLK
MDIO_MDIO
rft_clk
CORE_CLKOUTM4
(200 MHz)
gmii1_mtxd_o[7:4]
gmii1_gmtclk_o
gmii1_mtxd_o[3:0]
gmii1_mrxdv_I
gmii1_mrxer_I
gmii1_mcol_I
gmii1_mcrs_I
gmii1_mt_clk
gmii1_gmtxen_o
gmii1_mr_clk
gmii1_mrxd_i[3:0]
gmii1_mrxd_i[7:4]
GMII2_RXCLK
GMII2_RXD[3:0]
GMII2_RXDV
GMII2_RXER
GMII2_COL
GMII2_CRS
GMII2_TXD[3:0]
GMII2_TXCLK
GMII2_TXEN
gmii2_mtxd_o[7:4]
gmii2_mrxdv_i
gmii2_mrxer_i
gmii2_mcol_i
gmii2_mcrs_i
gmii2_mt_clk
gmii2_gmtxen_o
gmii2_mr_clk
RGMII2_TCLK
RGMII2_TCTL
RGMII2_TD[3:0]
RGMII2_RCLK
RGMII2_RCTL
RGMII2_RD[3:0]
rgmii2_txc_out_clk
rgmii2_tx_ctl_o
rgmii2_txd_o[3:0]
rgmii2_rxc_clk
rgmii2_rx_ctl_I
rgmii2_rxd_i[3:0]
RGMII1_TCLK
RGMII1_TCTL
RGMII1_TD[3:0]
RGMII1_RCLK
RGMII1_RCTL
RGMII1_RD[3:0]
rgmii1_txc_out_clk
rgmii1_tx_ctl_o
rgmii1_txd_o[3:0]
rgmii1_rxc_clk
rgmii1_rx_ctl_I
rgmii1_rxd_i[3:0]
RMII1_REFCLK
RMII1_TXD[1:0]
RMII1_RXERR
RMII1_RXD[1:0]
RMII2_REFCLK
RMII2_TXD[1:0]
RMII2_RXERR
RMII2_RXD[1:0]
Regs
S
S
S
S
main_clk
mhz_50_CLK
mhz_5_CLK
mhz_250_CLK
cpts_rft_clk
gmii2_sel[1:0]
gmii1_sel[1:0]
rgmii1_id_mode1_n
rgmii2_id_mode2_n
Control
Module
iso_main_arst_n
main_arst_n
hw1_ts_push
hw2_ts_push
hw3_ts_push
hw4_ts_push
DMTIMER4
DMTIMER5
DMTIMER6
DMTIMER7
0
1
/2
/2, /5
/10
CORE_CLKOUTM5
(250 MHz)
POTIMERPWM
POTIMERPWM
POTIMERPWM
POTIMERPWM
RMII2_CRS_DV
RMII1_CRS_DV
rmii2_txen_o
rmii2_txd_o[1:0]
rmii2_rxer_I
rmii2_rxd_i[1:0]
rmii2_crs_dv_I
rmii1_txen_o
rmii1_txd_o[1:0]
rmii1_rxer_I
rmii1_rxd_i[1:0]
rmii1_crs_dv_I
rgmii2_mii_mcol_I
rgmii2_mii_mcrs_I
rgmii2_mii_mrxer
rgmii2_txc_in_clk
rgmii2_mii_mcol_I
rgmii2_mii_mcrs_I
rgmii2_mii_mrxer_I
rgmii2_txc_in_clk
RMII1_TXEN
rmii1_mhz50_clk
RMII2_TXEN
rmii2_mhz50_clk
rmii1_io_clk_en
rmii1_io_clk_en
To RMII REFCLK
I/O Buffers
OHCP
Bridge
1_RXCLK
GMII_SEL
OHCP
Bridge
CPRGMII1
CPRGMII2
CPRMII1
CPRMII2
gmii2_gmtclk_o
gmii2_mrxd_i[3:0]
gmii2_mrxd_i[7:4]
gmii2_mtxd_o[3:0]
Integration
www.ti.com
14.2 Integration
This device includes a single instantiation of the three-port Gigabit Ethernet Switch Subsystem
(CPSW_3GSS_RG). The switch provides 2 external ethernet ports (ports 1 and 2) and an internal CPPI
interface port (port 0) with IEEE 1588v2 and 802.1ae support. The subsystem consists of:
• One instance of the 3-port Gigabit switch CPSW-3G, which contains:
– 2 CPGMAC_SL 10/100/1000 ethernet port modules with GMII interface
• Two RGMII interface modules
• Two RMII interface modules
• One MDIO interface module
• One Interrupt Controller module
• Local CPPI memory of size 8K Bytes
The integration of the Ethernet Switch is shown in Figure 14-1
Figure 14-1. Ethernet Switch Integration
1166
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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