Device
L3 Fast
Interconnect
TPTC
CFG Slave
dbs_pi[1:0]
Control
Module
MPU Subsystem
PRU-ICSS
Interrupts
erint_pend_po
int_pend_po
bigendian_pi
Master Read
Master Write
Completion
Port
L3 Fast
Interconnect
128
L3 Fast
Interconnect
128
To TPCC
Integration
www.ti.com
11.2.1.3 TPCC Pin List
The TPCC module does not include any external interface pins.
11.2.2 Third-Party Transfer Controller (TPTC) Integration
This device uses the three TPTC peripherals (TC0–TC2; TC3 is not supported) to perform EDMA
transfers between slave peripherals. The submission of transfer requests to the TPTCs is controlled by the
TPCC. Figure 11-3 shows the integration of the TPTC modules
Figure 11-3. TPTC Integration
11.2.2.1 TPTC Connectivity Attributes
The general connectivity attributes for the TPTCs are shown in Table 11-3.
Table 11-3. TPTC Connectivity Attributes
Attributes Type
Power domain Peripheral Domain
Clock domain PD_PER_L3_GCLK
Reset signals PER_DOM_RST_N
Idle/Wakeup signals Standby
Smart Idle
Interrupt request
Error interrupt per instance
erint_pend_po (TCERRINTx) – to MPU Subsystem and PRU-
ICSS (tptc_erint_pend_po, TPTC0 only)
DMA request none
Physical address L3 Fast slave port
11.2.2.2 TPTC Clock and Reset Management
The TPTC operates from a single clock and runs at the L3_Fast clock rate.
Table 11-4. TPTC Clock Signals
Clock Signal Max Freq Reference / Source Comments
tptc_clk_pi 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk
Interface / Functional clock From PRCM
874
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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