Texas Instruments AM335 Series Technical Reference Manual

Ethernet Subsystem Registers www.ti.com
14.5.2.31 DMA_INTSTAT_MASKED Register (offset = B4h) [reset = 0h]
DMA_INTSTAT_MASKED is shown in Figure 14-59 and described in Table 14-70.
CPDMA_INT DMA INTERRUPT STATUS REGISTER (MASKED VALUE)
Figure 14-59. DMA_INTSTAT_MASKED Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved HOST_PEND STAT_PEND
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-70. DMA_INTSTAT_MASKED Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 HOST_PEND R 0h
Host Pending Interrupt - masked interrupt read.
0 STAT_PEND R 0h
Statistics Pending Interrupt - masked interrupt read.
1290
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English