Ethernet Subsystem Registers
www.ti.com
14.5.3.5 CPTS_TS_LOAD_EN Register (offset = 14h) [reset = 0h]
CPTS_TS_LOAD_EN is shown in Figure 14-82 and described in Table 14-94.
TIME STAMP LOAD ENABLE REGISTER
Figure 14-82. CPTS_TS_LOAD_EN Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TS_LOAD_EN
R-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-94. CPTS_TS_LOAD_EN Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 TS_LOAD_EN W 0h Time Stamp Load - Writing a one to this bit enables the time stamp
value to be written via the ts_load_val[
31:0] register.
This feature is included for test purposes.
This bit is write only.
1314
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
