Interrupt Controller Registers
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6.5.1.1 INTC_REVISION Register (offset = 0h) [reset = 50h]
INTC_REVISION is shown in Figure 6-4 and described in Table 6-4.
This register contains the IP revision code
Figure 6-4. INTC_REVISION Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Rev
R-50h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-4. INTC_REVISION Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
Reads returns 0
7-0 Rev R 50h IP revision
[7:4] Major revision
[3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1
206
Interrupts SPRUH73H–October 2011–Revised April 2013
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