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20.4.4.1.15 WDT_WIRQENSET Register (offset = 5Ch) [reset = 0h]
WDT_WIRQENSET is shown in Figure 20-113 and described in Table 20-126.
In the Watchdog Interrupt Enable Set Register, IRQ enable set per-event interrupt enable bit vector, line 0.
Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register.
Figure 20-113. WDT_WIRQENSET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved ENABLE_DLY ENABLE_OVF
R-0h R/W1S-0h R/W1S-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-126. WDT_WIRQENSET Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 ENABLE_DLY R/W1S 0h
Enable for delay event
0x0x0(W) = No action
0x0x0(R) = Interrupt disabled (masked)
0x0x1(W) = Enable interrupt.
0x0x1(R) = Interrupt enabled
0 ENABLE_OVF R/W1S 0h
Enable for overflow event
0x0x0(W) = No action
0x0x0(R) = Interrupt disabled (masked)
0x0x1(W) = Enable interrupt.
0x0x1(R) = Interrupt enabled
3696
Timers SPRUH73H–October 2011–Revised April 2013
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