PRCM
L4 Wakeup
Interconnect
MPU Subsystem,
WakeM3
DMTIMER_DMC_1MS
(Timer1)
pieventcapt
portimerpwm
piclktimer
CLK_32KHZ
TCLKIN
porgpocfg
TIMER1_GCLK
pointr_pend
CLK_M_OSC
CLK_RC_32K
pointr_swakeup
WakeM3
CLK_32K_RTC
0
1
3
4
2
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DMTimer 1ms
20.2.2 Integration
Figure 20-27. DMTimer 1 ms Integration
20.2.2.1 Timer Connectivity Attributes
Table 20-28. Timer1 Connectivity Attributes
Attributes Type
Power Domain Wakeup Domain
Clock Domain PD_WKUP_L4_WKUP_GCLK (OCP)
PD_WKUP_TIMER1_GCLK (Func)
Reset Signals WKUP_DOM_RST_N
Idle/Wakeup Signals Smart Idle / Slave Wakeup
Interrupt Requests 1 to MPU Subsystem (TINT1_1MS) and WakeM3
DMA Requests None
Physical Address L4 Wakeup slave port
20.2.2.2 Timer Clock and Reset Manangement
The DMTimer1 1ms timer functional clock can be selected from one of five sources using the
CLKSEL_TIMER1MS_CLK register in the PRCM:
• The 24 MHz (typ) system clock (CLK_M_OSC)
• The PER PLL generated 32.768 KHz clock (CLK_32KHZ)
• The TCLKIN external timer input clock
• The on-chip ~32.768 KHz oscillator (CLK_RC32K)
• The external 32.768 KHz oscillator/clock (CLK_32K_RTC)
3587
SPRUH73H–October 2011–Revised April 2013 Timers
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