Ethernet Subsystem Registers
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14.5.3.3 CPTS_TS_PUSH Register (offset = Ch) [reset = 0h]
CPTS_TS_PUSH is shown in Figure 14-80 and described in Table 14-92.
TIME STAMP EVENT PUSH REGISTER
Figure 14-80. CPTS_TS_PUSH Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TS_PUSH
R-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-92. CPTS_TS_PUSH Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 TS_PUSH W 0h Time stamp event push - When a logic high is written to this bit a
time stamp event is pushed onto the event FIFO.
The time stamp value is the time of the write of this register, not the
time of the event read.
The time stamp value can then be read on interrupt via the event
registers.
Software should not push a second time stamp event onto the event
FIFO until the first time stamp value has been read from the event
FIFO (there should be only one time stamp event in the event FIFO
at any given time).
This bit is write only and always reads zero.
1312
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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