Ethernet Subsystem Registers
www.ti.com
14.5.2.11 EMCONTROL Register (offset = 2Ch) [reset = 0h]
EMCONTROL is shown in Figure 14-39 and described in Table 14-50.
CPDMA_REGS EMULATION CONTROL
Figure 14-39. EMCONTROL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved SOFT FREE
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-50. EMCONTROL Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 SOFT R/W 0h
Emulation Soft Bit
0 FREE R/W 0h
Emulation Free Bit
1270
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
