EDMA3 Registers
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11.4.1.2.4 QDMA Event Missed Clear Register (QEMCR)
Once a missed event is posted in the QDMA event missed registers (QEMR), the bit remains set and you
need to clear the set bit(s). This is done by way of CPU writes to the QDMA event missed clear registers
(QEMCR). Writing a 1 to any of the bits clears the corresponding missed event (bit) in QEMR; writing a 0
has no effect.
The QEMCR is shown in Figure 11-55 and described in Table 11-40.
Figure 11-55. QDMA Event Missed Clear Register (QEMCR)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 w-0 w-0 w-0 w-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 11-40. QDMA Event Missed Clear Register (QEMCR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
7-0 En QDMA event missed clear. All error bits must be cleared before additional error interrupts will be
asserted by the EDMA3CC.
0 No effect.
1 Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0).
11.4.1.2.5 EDMA3CC Error Register (CCERR)
The EDMA3CC error register (CCERR) indicates whether or not at any instant of time the number of
events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set
in the queue watermark threshold register (QWMTHRA). Additionally, CCERR also indicates if when the
number of outstanding TRs that have been programmed to return transfer completion code (TRs which
have the TCINTEN or TCCHEN bit in OPT set) to the EDMA3CC has exceeded the maximum allowed
value of 63. If any bit in CCERR is set (and all errors, including bits in other error registers (EMR/EMRH,
QEMR) were previously cleared), the EDMA3CC generates an error interrupt. For details on EDMA3CC
error interrupt generation, see Error Interrupts. Once the error bits are set in CCERR, they can only be
cleared by writing to the corresponding bits in the EDMA3CC error clear register (CCERRCLR).
The CCERR is shown in Figure 11-56 and described in Table 11-41.
Figure 11-56. EDMA3CC Error Register (CCERR)
31 17 16
Reserved TCCERR
R-0 R-0
15 4 3 2 1 0
Reserved QTHRXCD3 QTHRXCD2 QTHRXCD1 QTHRXCD0
R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
954
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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