Power, Reset, and Clock Management
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8.1.12.1.18 CM_PER_SPI0_CLKCTRL Register (offset = 4Ch) [reset = 30000h]
CM_PER_SPI0_CLKCTRL is shown in Figure 8-40 and described in Table 8-47.
This register manages the SPI0 clocks.
Figure 8-40. CM_PER_SPI0_CLKCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-47. CM_PER_SPI0_CLKCTRL Register Field Descriptions
Bit Field Type Reset Description
31-18 Reserved R 0h
17-16 IDLEST R 3h
Module idle status.
0x0 = Func : Module is fully functional, including OCP
0x1 = Trans : Module is performing transition: wakeup, or sleep, or
sleep abortion
0x2 = Idle : Module is in Idle mode (only OCP part). It is functional if
using separate functional clock
0x3 = Disable : Module is disabled and cannot be accessed
15-2 Reserved R 0h
1-0 MODULEMODE R/W 0h
Control the way mandatory clocks are managed.
0x0 = DISABLED : Module is disable by SW. Any OCP access to
module results in an error, except if resulting from a module wakeup
(asynchronous wakeup).
0x1 = RESERVED_1 : Reserved
0x2 = ENABLE : Module is explicitly enabled. Interface clock (if not
used for functions) may be gated according to the clock domain
state. Functional clocks are guarantied to stay present. As long as in
this configuration, power domain sleep transition cannot happen.
0x3 = RESERVED : Reserved
568
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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