I2C Registers
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21.4.1.18 I2C_DATA Register (offset = 9Ch) [reset = 0h]
I2C_DATA is shown in Figure 21-33 and described in Table 21-26.
This register is the entry point for the local host to read data from or write data to the FIFO buffer.
Figure 21-33. I2C_DATA Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-26. I2C_DATA Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 DATA R/W 0h Transmit/Receive data FIFO endpoint.
When read, this register contains the received I2C data.
When written, this register contains the byte value to transmit over
the I2C data.
In SYSTEST loop back mode (I2C_SYSTEST: TMODE = 11), this
register is also the entry/receive point for the data.
Values after reset are unknown (all
8-bits).
Note: A read access, when the buffer is empty, returns the previous
read data value.
A write access, when the buffer is full, is ignored.
In both events, the FIFO pointers are not updated and an Access
Error (AERR) Interrupt is generated.
3748
I2C SPRUH73H–October 2011–Revised April 2013
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