DMTimer
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20.1.5.8 IRQWAKEEN Register (offset = 34h) [reset = 0h]
IRQWAKEEN is shown in Figure 20-16 and described in Table 20-18.
Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup.
Figure 20-16. IRQWAKEEN Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_WUP_ENA OVF_WUP_ENA MAT_WUP_ENA
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-18. IRQWAKEEN Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 TCAR_WUP_ENA R/W 0h
Wakeup generation for Capture
0x0 = Wakeup disabled
0x1 = Wakeup enabled
1 OVF_WUP_ENA R/W 0h
Wakeup generation for Overflow
0x0 = Wakeup disabled
0x1 = Wakeup enabled
0 MAT_WUP_ENA R/W 0h
Wakeup generation for Match
0x0 = Wakeup disabled
0x1 = Wakeup enabled
3574
Timers SPRUH73H–October 2011–Revised April 2013
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