Interrupt Controller Registers
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6.5.1.9 INTC_IRQ_PRIORITY Register (offset = 60h) [reset = FFFFFFC0h]
INTC_IRQ_PRIORITY is shown in Figure 6-12 and described in Table 6-12.
This register supplies the currently active IRQ priority level
Figure 6-12. INTC_IRQ_PRIORITY Register
31 30 29 28 27 26 25 24
SpuriousIRQflag
R-1FFFFFFh
23 22 21 20 19 18 17 16
SpuriousIRQflag
R-1FFFFFFh
15 14 13 12 11 10 9 8
SpuriousIRQflag
R-1FFFFFFh
7 6 5 4 3 2 1 0
SpuriousIRQflag IRQPriority
R-1FFFFFFh R-40h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-12. INTC_IRQ_PRIORITY Register Field Descriptions
Bit Field Type Reset Description
31-7 SpuriousIRQflag R 1FFFFFFh
Spurious IRQ flag
6-0 IRQPriority R 40h
Current IRQ priority
214
Interrupts SPRUH73H–October 2011–Revised April 2013
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