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Ethernet Subsystem Registers
14.5.3.8 CPTS_INT_ENABLE Register (offset = 28h) [reset = 0h]
CPTS_INT_ENABLE is shown in Figure 14-85 and described in Table 14-97.
TIME SYNC INTERRUPT ENABLE REGISTER
Figure 14-85. CPTS_INT_ENABLE Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TS_PEND_EN
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-97. CPTS_INT_ENABLE Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 TS_PEND_EN R/W 0h
TS_PEND masked interrupt enable.
1317
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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