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EMIF
7.3.5.14 PWR_MGMT_CTRL_SHDW Register (offset = 3Ch) [reset = 0h]
PWR_MGMT_CTRL_SHDW is shown in Figure 7-104 and described in Table 7-124.
Figure 7-104. PWR_MGMT_CTRL_SHDW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved reg_pd_tim_shdw
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_sr_tim_shdw reg_cs_tim_shdw
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-124. PWR_MGMT_CTRL_SHDW Register Field Descriptions
Bit Field Type Reset Description
31-12 Reserved R 0h
11-8 reg_pd_tim_shdw R/W 0h Shadow field for reg_pd_tim.
This field is loaded into reg_pd_tim field in Power Management
Control register when SIdleAck is asserted.
7-4 reg_sr_tim_shdw R/W 0h Shadow field for reg_sr_tim.
This field is loaded into reg_sr_tim field in Power Management
Control register when SIdleAck is asserted.
3-0 reg_cs_tim_shdw R/W 0h Shadow field for reg_cs_tim.
This field is loaded into reg_cs_tim field in Power Management
Control register when SIdleAck is asserted.
439
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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