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Functional Description
26.1.7.2 XIP Memory
The ROM Code can boot directly from XIP devices. A typical XIP device is a NOR flash memory. Support
for XIP devices is performed under the following assumptions:
• Uses GPMC as the communication interface
• Up to 1Gbit (128Mbytes) memories can be connected
• Both x8 and x16 data bus width
• Asynchronous protocol
• Supports address/data multiplexed mode and non-muxed mode
• GPMC clock is 50-MHz
• Device connected to CS0 mapped to address 0x08000000.
• Wait pin signal WAIT0 monitored depending on the SYSBOOT pin configuration (XIP / XIP w/ WAIT).
• Flexible muxing options for gpmc_a0-gpmc_a11 for non-muxed XIP devices
Depending on the SYSBOOT pins, the GPMC is configured to use the WAIT signal connected on the
WAIT0 pin or not. Wait pin polarity is set to stall accessing memory when the WAIT0 pin is low. The wait
monitoring is intended to be used with memories which require long time for initialization after reset or
need to pause while reading data. The boot procedure from XIP device can be described as such:
• Configure GPMC for XIP device access.
• Set the image location to 0x08000000.
• Verify if bootable image is present at the image location.
• If the image has been found, start the execution.
• If the image has not been found, return from XIP booting to the main booting loop.
26.1.7.2.1 XIP Initialization and Detection
• GPMC initialization
Figure 26-9 and Table 26-8 describe the GPMC timing settings set for XIP boot and other address-data
accessible devices.
4115
SPRUH73H–October 2011–Revised April 2013 Initialization
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