DMTimer 1ms
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20.2.5.4 TISR Register (offset = 18h) [reset = 0h]
TISR is shown in Figure 20-38 and described in Table 20-39.
The Timer Status Register is used to determine which of the timer events requested an interrupt.
Figure 20-38. TISR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_IT_FLAG OVF_IT_FLAG MAT_IT_FLAG
R-0h R/W1toCl-0h R/W1toCl-0h R/W1toCl-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-39. TISR Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
Reads return 0
2 TCAR_IT_FLAG R/W1toCl 0h
indicates when an external pulse transition of the correct polarity is
detected on the external pin PIEVENTCAPT
0 = TCAR_IT_FLAG_0 : no capture interrupt request
1 = TACR_IT_FLAG_1 : capture interrupt request
1 OVF_IT_FLAG R/W1toCl 0h
TCRR overflow
0 = OVF_IT_FLAG_0 : no overflow interrupt request
1 = OVF_IT_FLAG_1 : overflow interrupt pending
0 MAT_IT_FLAG R/W1toCl 0h
the compare result of TCRR and TMAR
0 = MAT_IT_FLAG_0 : no compare interrupt request
1 = MAT_IT_FLAG_1 : compare interrupt pending
3602
Timers SPRUH73H–October 2011–Revised April 2013
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