EDMA3 Registers
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11.4.2.7.15 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
The destination FIFO memory protection proxy register (DFMPPRXYn) is shown in Figure 11-129 and
described in Table 11-105.
Figure 11-129. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
31 16
Reserved
R-0
15 9 8 7 4 3 0
Reserved PRIV Reserved PRIVID
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-114. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field
Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
8 PRIV Privilege level. This contains the Privilege level used by the EDMA3 programmer to set up the
parameter entry in the channel controller. This field is set up when the associated TR is submitted to the
EDMA3TC.
The privilege ID is used while issuing read and write command to the target endpoints so that the target
endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA
transaction.
0 User-level privilege
1 Supervisor-level privilege
7-4 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
3-0 PRIVID 0-Fh Privilege ID. This contains the Privilege ID of the EDMA3 programmer that set up the parameter entry in
the channel controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
1016
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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