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DCAN Registers
23.4.17 NWDAT56 Register (offset = A4h) [reset = 0h]
NWDAT56 is shown in Figure 23-35 and described in Table 23-30.
These registers hold the NewDat bits of the implemented message objects. By reading out these bits, the
CPU can check for new data in the message objects. The NewDat bit of a specific message object can be
set/reset by the CPU via the IF1/IF2 interface register sets, or by the message handler after reception of a
data frame or after a successful transmission.
Figure 23-35. NWDAT56 Register
31 30 29 28 27 26 25 24
NewDat[96:81]
R-0h
23 22 21 20 19 18 17 16
NewDat[96:81]
R-0h
15 14 13 12 11 10 9 8
NewDat[80:65]
R-0h
7 6 5 4 3 2 1 0
NewDat[80:65]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-30. NWDAT56 Register Field Descriptions
Bit Field Type Reset Description
31-16 NewDat[96:81] R 0h
New Data Bits (for all message objects)
0x0 = No new data has been written into the data portion of this
message object by the message handler since the last time when
this flag was cleared by the CPU.
0x1 = The message handler or the CPU has written new data into
the data portion of this message object.
15-0 NewDat[80:65] R 0h
New Data Bits (for all message objects)
0x0 = No new data has been written into the data portion of this
message object by the message handler since the last time when
this flag was cleared by the CPU.
0x1 = The message handler or the CPU has written new data into
the data portion of this message object.
3943
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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