Programming Model
www.ti.com
13.4 Programming Model
13.4.1 LCD Character Displays
13.4.1.1 Configuration Registers, Setup, and Settings
13.4.1.1.1 Configuration Registers
Set the following to appropriate values for the target LCD character panel:
• cfg_cs1_e1_pol
• cfg_cs0_e0_pol
• ws_dir_pol
• cfg_rs_en_pol
• cfg_alepol
cfg_lidd_mode_sel[2:0] defines the type of CPU bus that will be used in interfacing with the LCD character
panel. Note that the clocked bus styles only support a single panel using CS0 since the clock pin takes a
device pin that is otherwise used for CS1.
Set the following to appropriate bus timing parameters for the target LCD character panel:
• cfg_w_su
• cfg_w_strobe
• cfg_w_hold, cfg_r_su
• cfg_r_strobe
• cfg_r_hold
• cfg_ta
A set of bus timing parameters are individually available for CS0 and CS1 such that the bus transactions
can be customized for each of the two supported LCD character displays.
13.4.1.1.2 Defining Panel Commands and Panel Data
In the Hitachi interface mode used for the example panel, whether the Character Panel understands a
data transfer as Command or Data depends on the state of the REGSEL input pin. Writing to the
cfg_adr_indx register will output a Command transfer. Writing to the cfg_data register will result in a Data
transfer.
Functionally, the ALE (lcd_fp pin) from the LCD controller is tied to the REGSEL input of the character
panel.
For example, to send byte 0xAB as a command to the previously described character panel, the CPU
would write 0x00AB to the adr_indx register. To send byte 0xAB as data, the CPU would write 0x00AB to
the data register.
1122
LCD Controller SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
