GPMC
www.ti.com
7.1.3.3.10 NOR Access Description
For each chip-select configuration, the read access can be specified as either asynchronous or
synchronous access through the GPMC_CONFIG1_i[29] READTYPE bit. For each chip-select
configuration, the write access can be specified as either synchronous or asynchronous access through
the GPMC_CONFIG1_i[27] WRITETYPE bit.
Asynchronous and synchronous read and write access time and related control signals are controlled
through timing parameters that refer to GPMC_FCLK. The primary difference of synchronous mode is the
availability of a configurable clock interface (GPMC_CLK) to control the external device. Synchronous
mode also affects data-capture and wait-pin monitoring schemes in read access.
For details about asynchronous and synchronous access, see the descriptions of GPMC_CLK,
RdAccessTime, WrAccessTime, and wait-pin monitoring.
For more information about timing-parameter settings, see the sample timing diagrams in this chapter.
The address bus and BE[1:0]n are fixed for the duration of a synchronous burst read access, but they are
updated for each beat of an asynchronous page-read access.
7.1.3.3.10.1 Asynchronous Access Description
This section describes:
• Asynchronous single read operation on an address/data multiplexed device
• Asynchronous single write operation on an address/data-multiplexed device
• Asynchronous single read operation on an AAD-multiplexed device
• Asynchronous single write operation on an AAD-multiplexed device
• Asynchronous multiple (page) read operation on a non-multiplexed device
In asynchronous operations GPMC_CLK is not provided outside the GPMC and is kept low.
280
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
