Texas Instruments AM335 Series Technical Reference Manual

Functional Description www.ti.com
Table 19-12. IrDA Mode Interrupts (continued)
UART_IIR Bit Interrupt Type Interrupt Source Interrupt Reset Method
2 Last byte in RX FIFO Last byte of frame in RX FIFO Read the UART_RHR register.
is available to be read at the
RHR port.
3 RX overrun Write to the UART_RHR Read UART_RESUME register.
register when the RX FIFO is
full.
4 Status FIFO interrupt Status FIFO triggers level Read STATUS FIFO.
reached.
5 TX status
1. UART_THR empty before 1. Read the UART_RESUME register.
EOF sent. Last bit of OR
transmission of the IrDA
2. Read the UART_IIR register.
frame occurred, but with
an underrun error.
OR
2. Transmission of the last bit
of the IrDA frame
completed successfully.
6 Receiver line status interrupt CRC, ABORT, or frame-length Read the STATUS FIFO (read until empty
error is written into the - maximum of eight reads required).
STATUS FIFO.
7 Received EOF Received end-of-frame Read the UART_IIR register.
19.3.5.4 CIR Mode Interrupt Management
19.3.5.4.1 CIR Interrupts
The CIR function generates interrupts that can be enabled and disabled by writing to the appropriate bit in
the interrupt enable register (UARTi.UART_IER). The interrupt status of the device can be checked by
reading the interrupt identification register (UARTi.UART_IIR).
UART, IrDA, and CIR modes have different interrupts in the UART/IrDA/CIR module and, therefore,
different UARTi.UART_IER and UARTi.UART_IIR mappings, depending on the selected mode.
Table 19-13 lists the interrupt modes to be maintained. In CIR mode, the sole purpose of the
UARTi.UART_IIR[5] bit is to indicate that the last bit of infrared data was passed to the uart_cts_rctx pin.
Table 19-13. CIR Mode Interrupts
UART_IIR Bit Interrupt Type Interrupt Source Interrupt Reset Method
Number
0 RHR interrupt DRDY (data ready) (FIFO disable) Read UART_RHR until interrupt condition
disappears.
RX FIFO above trigger level (FIFO
enable)
1 THR interrupt TFE (UART_THR empty) (FIFO Write to the UART_THR register until the
disable) interrupt condition disappears.
TX FIFO below trigger level (FIFO
enable)
2 RX_STOP_IT Receive stop interrupt (depending Read IIR
on value set in the BOF Length
Register (UART_EBLR).
3 RX overrun Write to RHR when RX FIFO is full. Read RESUME register.
4 N/A for CIR mode N/A for CIR mode N/A for CIR mode
5 TX status Transmission of the last bit of the Read the UART_IIR register.
frame is complete successfully.
6 N/A for CIR mode N/A for CIR mode N/A for CIR mode
7 N/A for CIR mode N/A for CIR mode N/A for CIR mode
3458
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated

Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English