Power, Reset, and Clock Management
www.ti.com
8.1.13.8.1 PM_CEFUSE_PWRSTCTRL Register (offset = 0h) [reset = 0h]
PM_CEFUSE_PWRSTCTRL is shown in Figure 8-193 and described in Table 8-215.
This register controls the CEFUSE power state to reach upon a domain sleep transition
Figure 8-193. PM_CEFUSE_PWRSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerStateChang Reserved PowerState
e
R-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-215. PM_CEFUSE_PWRSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-5 Reserved R 0h
4 LowPowerStateChange R/W 0h Power state change request when domain has already performed a
sleep transition.
Allows going into deeper low power state without waking up the
power domain.
0x0 = DIS : Do not request a low power state change.
0x1 = EN : Request a low power state change. This bit is
automatically cleared when the power state is effectively changed or
when power state is ON.
3-2 Reserved R 0h
1-0 PowerState R/W 0h
Power state control
0x0 = OFF : OFF state
0x1 = Reserved : Reserved
0x2 = INACT : INACTIVE state
0x3 = ON : ON State
744
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
