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LCD Registers
13.5.2 CTRL Register (offset = 4h) [reset = 0h]
CTRL is shown in Figure 13-20 and described in Table 13-15.
Figure 13-20. CTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
clkdiv
R/W-0h
7 6 5 4 3 2 1 0
Reserved auto_uflow_restart modesel
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 13-15. CTRL Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-8 clkdiv R/W 0h Clock divisor
Raster mode: Values of 2 through 255 are permitted and resulting
pixel clock is lcd_clk/2 through lcd_clk/255
LIDD mode: Values of 0 through 255 are permitted with resulting
MCLK of lcd_clk/1 through lcd_clk/255 where both 0 and 1 result in
lcd_clk/1
7-2 Reserved R/W 0h
1 auto_uflow_restart R/W 0h
0 = On an underflow, the software has to restart the module 1 = On
an underflow, the hardware will restart on the next frame
0 modesel R/W 0h LCD Mode select
0 = LCD Controller in LIDD Mode 1 = LCD Controller in Raster Mode
1131
SPRUH73H–October 2011–Revised April 2013 LCD Controller
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