DCAN Registers
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23.4.14 NWDAT_X Register (offset = 98h) [reset = 0h]
NWDAT_X is shown in Figure 23-32 and described in Table 23-27.
With the new data X register, the CPU can detect if one or more bits in the different new data registers are
set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits of
these message objects are set, the corresponding bit in the new data X register will be set. Example 1. Bit
0 of the new data X register represents byte 0 of the new data 1 register. If one or more bits in this byte
are set, bit 0 of the new data X register will be set.
Figure 23-32. NWDAT_X Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
NewDatReg8 NewDatReg7 NewDatReg6 NewDatReg5
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
NewDatReg4 NewDatReg3 NewDatReg2 NewDatReg1
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-27. NWDAT_X Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-14 NewDatReg8 R 0h
NewDatReg8
13-12 NewDatReg7 R 0h
NewDatReg7
11-10 NewDatReg6 R 0h
NewDatReg6
9-8 NewDatReg5 R 0h
NewDatReg5
7-6 NewDatReg4 R 0h
NewDatReg4
5-4 NewDatReg3 R 0h
NewDatReg3
3-2 NewDatReg2 R 0h
NewDatReg2
1-0 NewDatReg1 R 0h
NewDatReg1
3940
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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