USB Registers
www.ti.com
16.5.3.10 USB1IRQENABLESET1 Register (offset = 3Ch) [reset = 0h]
USB1IRQENABLESET1 is shown in Figure 16-108 and described in Table 16-118.
Figure 16-108. USB1IRQENABLESET1 Register
31 30 29 28 27 26 25 24
TX_FIFO_15 TX_FIFO_14 TX_FIFO_13 TX_FIFO_12 TX_FIFO_11 TX_FIFO_10 TX_FIFO_9 TX_FIFO_8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
TX_FIFO_7 TX_FIFO_6 TX_FIFO_5 TX_FIFO_4 TX_FIFO_3 TX_FIFO_2 TX_FIFO_1 Reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved USB_9 USB_8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
USB_7 USB_6 USB_5 USB_4 USB_3 USB_2 USB_1 USB_0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-118. USB1IRQENABLESET1 Register Field Descriptions
Bit Field Type Reset Description
31 TX_FIFO_15 R/W 0h
Interrupt enable for TX FIFO endpoint 15
30 TX_FIFO_14 R/W 0h
Interrupt enable for TX FIFO endpoint 14
29 TX_FIFO_13 R/W 0h
Interrupt enable for TX FIFO endpoint 13
28 TX_FIFO_12 R/W 0h
Interrupt enable for TX FIFO endpoint 12
27 TX_FIFO_11 R/W 0h
Interrupt enable for TX FIFO endpoint 11
26 TX_FIFO_10 R/W 0h
Interrupt enable for TX FIFO endpoint 10
25 TX_FIFO_9 R/W 0h
Interrupt enable for TX FIFO endpoint 9
24 TX_FIFO_8 R/W 0h
Interrupt enable for TX FIFO endpoint 8
23 TX_FIFO_7 R/W 0h
Interrupt enable for TX FIFO endpoint 7
22 TX_FIFO_6 R/W 0h
Interrupt enable for TX FIFO endpoint 6
21 TX_FIFO_5 R/W 0h
Interrupt enable for TX FIFO endpoint 5
20 TX_FIFO_4 R/W 0h
Interrupt enable for TX FIFO endpoint 4
19 TX_FIFO_3 R/W 0h
Interrupt enable for TX FIFO endpoint 3
18 TX_FIFO_2 R/W 0h
Interrupt enable for TX FIFO endpoint 2
17 TX_FIFO_1 R/W 0h
Interrupt enable for TX FIFO endpoint 1
9 USB_9 R/W 0h
Interrupt enable for Mentor controller USB_INT generic interrupt
8 USB_8 R/W 0h
Interrupt enable for DRVVBUS level change
7 USB_7 R/W 0h Interrupt enable for VBUS andlt
VBUS valid threshold
6 USB_6 R/W 0h
Interrupt enable for SRP detected
5 USB_5 R/W 0h
Interrupt enable for device disconnected (host mode)
4 USB_4 R/W 0h
Interrupt enable for device connected (host mode)
3 USB_3 R/W 0h
Interrupt enable for SOF started
2 USB_2 R/W 0h
Interrupt enable for Reset signaling detected (peripheral mode)
Babble detected (host mode)
1 USB_1 R/W 0h
Interrupt enable for Resume signaling detected
1870
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
