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7.3.5.12 SDRAM_TIM_3_SHDW Register (offset = 2Ch) [reset = 0h]
SDRAM_TIM_3_SHDW is shown in Figure 7-102 and described in Table 7-122.
Figure 7-102. SDRAM_TIM_3_SHDW Register
31 30 29 28 27 26 25 24
reg_t_pdll_ul_shdw Reserved
R/W-0h R-0h
23 22 21 20 19 18 17 16
Reserved reg_zq_zqcs_shdw
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
reg_zq_zqcs Reserved reg_t_rfc
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
reg_t_rfc_shdw reg_t_ras_max_shdw
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-122. SDRAM_TIM_3_SHDW Register Field Descriptions
Bit Field Type Reset Description
31-28 reg_t_pdll_ul_shdw R/W 0h Shadow field for reg_t_pdll_ul. This field is loaded into reg_t_pdll_ul
field in SDRAM Timing 3 register when SIdleAck is asserted.
27-24 Reserved R 0h
23-21 Reserved R/W 0h
Reserved.
20-15 reg_zq_zqcs_shdw R/W 0h Shadow field for reg_zq_zqcs. This field is loaded into reg_zq_zqcs
field in SDRAM Timing 3 register when SIdleAck is asserted.
14-13 Reserved R/W 0h
Reserved.
12-4 reg_t_rfc_shdw R/W 0h Shadow field for reg_t_rfc. This field is loaded into reg_t_rfc field in
SDRAM Timing 3 register when SIdleAck is asserted.
3-0 reg_t_ras_max_shdw R/W 0h Shadow field for reg_t_ras_max. This field is loaded into
reg_t_ras_max field in SDRAM Timing 3 register when SIdleAck is
asserted.
436
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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