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Ethernet Subsystem Registers
14.5.1.6 TBLW2 Register (offset = 34h) [reset = 0h]
TBLW2 is shown in Figure 14-20 and described in Table 14-30.
ADDRESS LOOKUP ENGINE TABLE WORD 2 REGISTER
Figure 14-20. TBLW2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ENTRY71-64
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-30. TBLW2 Register Field Descriptions
Bit Field Type Reset Description
7-0 ENTRY71-64 R/W-0 0 Table entry bits
71:64
1247
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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