Power, Reset, and Clock Management
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8.1.12.2.41 CM_DIV_M2_DPLL_DDR Register (offset = A0h) [reset = 1h]
CM_DIV_M2_DPLL_DDR is shown in Figure 8-124 and described in Table 8-132.
This register provides controls over the M2 divider of the DPLL.
Figure 8-124. CM_DIV_M2_DPLL_DDR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved ST_DPLL_CLKOUT DPLL_CLKOUT_GAT
E_CTRL
R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved DPLL_CLKOUT_DIVC DPLL_CLKOUT_DIV
HACK
R-0h R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-132. CM_DIV_M2_DPLL_DDR Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9 ST_DPLL_CLKOUT R 0h
DPLL CLKOUT status
0x0 = CLK_GATED : The clock output is gated
0x1 = CLK_ENABLED : The clock output is enabled
8 DPLL_CLKOUT_GATE_C R/W 0h
Control gating of DPLL CLKOUT
TRL
0x0 = CLK_AUTOGATE : Automatically gate this clock when there is
no dependency for it
0x1 = CLK_ENABLE : Force this clock to stay enabled even if there
is no request
7-6 Reserved R 0h
5 DPLL_CLKOUT_DIVCHA R 0h
Toggle on this status bit after changing DPLL_CLKOUT_DIV
CK
indicates that the change in divider value has taken effect
4-0 DPLL_CLKOUT_DIV R/W 1h
DPLL M2 post-divider factor (1 to 31).
660
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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