XCLK
(to Figure 17)
XCLK
CLKXP
(ACLKXCTL.7)
(polarity)
0
1
0
1
CLKXM
(internal/external)
(ACLKXCTL.5)
Pin Muxing
ACLKX
pin
0
1
0
1
AHCLKX_IN
AHCLKX_OUT
HCLKXM
(AHCLKXCTL.15)
HCLKXP
(AHCLKXCTL.14)
Divider
/1.../32
CLKXDIV
(ACLKXCTL[4-0])
Divider
/1.../4096
HCLKXDIV
(AHLKXCTL[11-0])
AUXCLK
Functional Description
www.ti.com
22.3.5.1 Transmit Clock
The transmit bit clock, ACLKX, (Figure 22-17) may be either externally sourced from the ACLKX pin or
internally generated, as selected by the CLKXM bit. If internally generated (CLKXM = 1), the clock is
divided down by a programmable bit clock divider (CLKXDIV) from the transmit high-frequency master
clock (AHCLKX).
Internally, the McASP always shifts transmit data at the rising edge of the internal transmit clock, XCLK,
(Figure 22-17). The CLKXP mux determines if ACLKX needs to be inverted to become XCLK. If
CLKXP = 0, the CLKXP mux directly passes ACLKX to XCLK. As a result, the McASP shifts transmit data
at the rising edge of ACLKX. If CLKXP = 1, the CLKX mux passes the inverted version of ACLKX to
XCLK. As a result, the McASP shifts transmit data at the falling edge of ACLKX.
The transmit high-frequency master clock, AHCLKX, may be either externally sourced from the AHCLKX
pin or internally generated, as selected by the HCLKXM bit. If internally generated (HCLKXM = 1), the
clock is divided down by a programmable high clock divider (HCLKXDIV) from McASP internal clock
source AUXCLK. The transmit high-frequency master clock may be (but is not required to be) output on
the AHCLKX pin where it is available to other devices in the system.
The transmit clock configuration is controlled by the following registers:
• ACLKXCTL.
• AHCLKXCTL.
Figure 22-17. Transmit Clock Generator Block Diagram
3784
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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