Functional Description
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16.3.8.2.2.2.2 Bulk OUT Operation: Host Mode
When Bulk data is required to be sent to the USB peripheral device, the software should write the first
packet of the data to the FIFO (or two packets if double-buffered) and set the TXPKTRDY bit in the
corresponding HOST_TXCSR register (bit 0). The controller will then send an OUT token to the selected
peripheral endpoint, followed by the first data packet from the FIFO.
If data is correctly received by the peripheral device, an ACK should be received whereupon the controller
will clear TXPKTRDY bit of HOST_TXCSR (bit 0). If the USB peripheral device responds with a STALL,
the RXSTALL bit (bit 5) of HOST_TXCSR is set. If a NAK is received, the controller tries again and
continues to try until either the transaction is successful or the NAK limit set in the HOST_TXINTERVAL
register is reached. If no response at all is received, two further attempts are made before the controller
reports an error by setting ERROR bit in HOST_TXCSR (bit 2).
The controller then generates the appropriate endpoint interrupt, whereupon the software should read the
corresponding HOST_TXCSR register to determine whether the RXSTALL (bit 5), ERROR (bit 2) or
NAK_TIMEOUT (bit 7) bit is set and act accordingly. If the NAK_TIMEOUT bit is set, the controller can be
directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT
bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
If large blocks of data are being transferred, then the overhead of calling an interrupt service routine to
load each packet can be avoided by using DMA.
16.3.8.2.2.2.3 Bulk OUT Error Handling: Host Mode
If the target wants to shut down the Bulk OUT pipe, it will send a STALL response. This is indicated by the
RXSTALL bit of HOST_TXCSR register (bit 5) being set.
16.3.8.2.3 Interrupt Transfer: Host Mode
When the controller is operating as the host, interactions with an Interrupt endpoint on the USB peripheral
device are handled in very much the same way as the equivalent Bulk transactions (described in previous
sections).
The principal difference as far as operational steps are concerned is that the PROT field of
HOST_RXTYPE and HOST_TXTYPE (bits 5-4) need to be set (binary value) to represent an Interrupt
transaction. The required polling interval also needs to be set in the HOST_RXINTERVAL and
HOST_TXINTERVAL registers.
16.3.8.2.4 Isochronous Transfer: Host Mode
Isochronous transfers are used when working with isochronous data. Isochronous transfers provide
periodic, continuous communication between host and device.
An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host.
16.3.8.2.4.1 Isochronous IN Transactions: Host Mode
The following optional features are available for use with an Rx endpoint used in Host mode to receive this
data:
• Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. This allows that one packet can be received while another is being read. Double packet
buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
• AutoRequest: When the AutoRequest feature is enabled, the REQPKT bit of HOST_RXCSR (bit 5) will
be automatically set when the RXPKTRDY bit is cleared. This only applies when the CPU is being
used to service the endpoint. When using DMA, this bit field needs to be cleared to Zero. CPPI DMA
has its own configuration registers that renders a similar task, USB0/1 Auto Req registers, that needs
to be used to have a similar effect. For more information, see Section 16.3.9, Communications Port
Programming Interface (CPPI) 4.1 DMA.
• DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention. However, this feature is not particularly useful with isochronous
1730
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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