EMIF
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12. Power Management Control Shadow register (PMCSR)
13. Interface Configuration register (INT_CONFIG)
14. System OCP Interrupt Enable Set Register (SOIESR)
15. DDR PHY Control 1 register (DDRPHYCR)
16. DDR PHY Control 1 Shadow register (DDRPHYCSR)
• Memory controller completes all pending transactions and drains all its FIFOs.
• Memory controller puts the SDRAM in Self Refresh.
• Memory controller copies all shadow memory mapped registers to its main registers. It is assumed that
the shadow register always has the same value as its corresponding main register.
• Memory controller waits for all interrupts to be serviced.
• Memory controller acknowledges assertion of internal power down request.
• The internal module reset signal is asserted.
• The clocks and power to the memory controller can now be switched off.
To restore power to the memory controller, the following sequence of operations is followed:
• The power and clocks to the Memory controller are switched on.
• The internal module reset signal is deasserted, indicating to the Memory controller that it is waking up
from off mode.
• The memory controller does not perform SDRAM initialization and forces its state machine to be in
self-refresh.
• The external master restores all of the above memory mapped registers.
• The external master restores all of the above memory mapped registers.
• The system can now perform access to the external memory.
7.3.3.11.6 EMIF PHY Clock Gating
The clock to the DDR2/3/mDDR PHY can be gated off to achieve power saving. For more information, see
the EMIF0/1 Clock Gate Control register (EMIF_CLK_GATE).
7.3.4 Use Cases
For details on connecting this device to mDDR/DDR2/DDR3 devices, see the device-specific data sheet,
which will include specific instructions and routing guidelines for interfacing to mDDR (LPDDR), DDR2,
and DDR3 devices.
7.3.5 EMIF4D Registers
Table 7-110 lists the memory-mapped registers for the EMIF4D. All register offset addresses not listed in
Table 7-110 should be considered as reserved locations and the register contents should not be modified.
Table 7-110. EMIF4D REGISTERS
Offset Acronym Register Name Section
0h EMIF_MOD_ID_REV Section 7.3.5.1
4h STATUS Section 7.3.5.2
8h SDRAM_CONFIG Section 7.3.5.3
Ch SDRAM_CONFIG_2 Section 7.3.5.4
10h SDRAM_REF_CTRL Section 7.3.5.5
14h SDRAM_REF_CTRL_SHDW Section 7.3.5.6
18h SDRAM_TIM_1 Section 7.3.5.7
1Ch SDRAM_TIM_1_SHDW Section 7.3.5.8
20h SDRAM_TIM_2 Section 7.3.5.9
24h SDRAM_TIM_2_SHDW Section 7.3.5.10
422
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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