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EMIF
Table 7-110. EMIF4D REGISTERS (continued)
Offset Acronym Register Name Section
28h SDRAM_TIM_3 Section 7.3.5.11
2Ch SDRAM_TIM_3_SHDW Section 7.3.5.12
38h PWR_MGMT_CTRL Section 7.3.5.13
3Ch PWR_MGMT_CTRL_SHDW Section 7.3.5.14
54h INT_CONFIG Interface Configuration Register Section 7.3.5.15
58h INT_CFG_VAL_1 Interface Configuration Value 1 Register Section 7.3.5.16
5Ch INT_CFG_VAL_2 Interface Configuration Value 2 Register Section 7.3.5.17
80h PERF_CNT_1 Section 7.3.5.18
84h PERF_CNT_2 Section 7.3.5.19
88h PERF_CNT_CFG Section 7.3.5.20
8Ch PERF_CNT_SEL Section 7.3.5.21
90h PERF_CNT_TIM Section 7.3.5.22
98h READ_IDLE_CTRL Section 7.3.5.23
9Ch READ_IDLE_CTRL_SHDW Section 7.3.5.24
A4h IRQSTATUS_RAW_SYS Section 7.3.5.25
ACh IRQSTATUS_SYS Section 7.3.5.26
B4h IRQENABLE_SET_SYS Section 7.3.5.27
BCh IRQENABLE_CLR_SYS Section 7.3.5.28
C8h ZQ_CONFIG Section 7.3.5.29
D4h RDWR_LVL_RMP_WIN Read-Write Leveling Ramp Window Register Section 7.3.5.30
D8h RDWR_LVL_RMP_CTRL Read-Write Leveling Ramp Control Register Section 7.3.5.31
DCh RDWR_LVL_CTRL Read-Write Leveling Control Register Section 7.3.5.32
E4h DDR_PHY_CTRL_1 Section 7.3.5.33
E8h DDR_PHY_CTRL_1_SHDW Section 7.3.5.34
100h PRI_COS_MAP Priority to Class of Service Mapping Register Section 7.3.5.35
104h CONNID_COS_1_MAP Connection ID to Class of Service 1 Mapping Register Section 7.3.5.36
108h CONNID_COS_2_MAP Connection ID to Class of Service 2 Mapping Register Section 7.3.5.37
120h RD_WR_EXEC_THRSH Read Write Execution Threshold Register Section 7.3.5.38
423
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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