www.ti.com
DMTimer
20.1.3.2 Accessing Registers
All registers are 32-bit wide, accessible via OCP interface with 16-bit or 32-bit OCP access (Read/Write).
The 32-bit registers write update in 16 bits access must be LSB16 first and the second write access must
be MSB16. For the write operation, the module allows skipping the MSB access if the user does not need
to update the 16 MSB bits of the register, but only for the OCP registers (TIDR, TIOCP_CFG,
IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR, IRQWAKEEN and TSICR). The
write operation on any functional register (TCLR, TCRR, TLDR, TTGR and TMAR) must be complete (the
MSB must be written even if the MSB data is not used).
20.1.3.2.1 Programming the Timer Registers
The TLDR, TCRR, TCLR, TIOCP_CFG, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR,
IRQWAKEEN, TTGR, TSICR and TMAR registers write is done synchronously with OCP clock, by the
host, using the OCP bus protocol.
20.1.3.2.2 Reading the Timer Registers
The counter register (TCRR) is a 32-bit “atomic datum” and 16-bit capture is done on the 16-bit LSB first
to allow atomic LSB16 + MSB16 capture. Atomic capture is also performed for the TCAR1 and TCAR2
registers as they may change due to internal processes. DSP 16 bit accesses can be interleaved with
MCU 32 bit accesses.
20.1.3.2.3 OCP Error Generation
The timer module responds with error indication in the following cases:
Error on write transactions
• Assert the PORSRESP = ERR signal in the same cycle as PORSCMDACCEPTED.
• Use the ERR code for PORSRESP during the response phase.
Error on read transactions
• Assert the PORSRESP = ERR signal in the same cycle as PORSCMDACCEPTED.
• Use the ERR code for PORSRESP during the response phase. PORSDATA in this case is not valid.
Table 20-9. OCP Error Reporting
Error Type Response: SRESP = ERR
Unsupported PIOCPMCMD command Yes
Address error: Read or write to a non-existing internal address No
Read to write-only registers and write to read-only registers No
Unaligned address (PIOCPMADDR ≠ 00) on read/write Yes
transaction
Unsupported PIOCPMBYTEEN on read/write transaction Yes
NOTE: Byte enable “0000” is a supported byte enable.
20.1.3.3 Posted Mode Selection
A choice between the two synchronization modes will be made taking into account the frequency ratio and
the stall periods that can be supported by the system, without impacting the global performance.
The posted mode selection applies only to functional registers that require synchronization on/from timer
clock domain. For write operation the registers affected by this posted/non-posted selection are: TCLR,
TLDR, TCRR, TTGR and TMAR. For read operation the register affected by this posted/non-posted
selection are: TCRR, TCAR1 and TCAR2.
3563
SPRUH73H–October 2011–Revised April 2013 Timers
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
