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Ethernet Subsystem Registers
14.5.2.30 DMA_INTSTAT_RAW Register (offset = B0h) [reset = 0h]
DMA_INTSTAT_RAW is shown in Figure 14-58 and described in Table 14-69.
CPDMA_INT DMA INTERRUPT STATUS REGISTER (RAW VALUE)
Figure 14-58. DMA_INTSTAT_RAW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved HOST_PEND STAT_PEND
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-69. DMA_INTSTAT_RAW Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 HOST_PEND R 0h
Host Pending Interrupt - raw int read (before mask).
0 STAT_PEND R 0h
Statistics Pending Interrupt - raw int read (before mask).
1289
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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