Power, Reset, and Clock Management
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8.1.12.3.10 CLKSEL_GFX_FCLK Register (offset = 2Ch) [reset = 0h]
CLKSEL_GFX_FCLK is shown in Figure 8-147 and described in Table 8-156.
Selects the divider value for GFX clock [warm reset insensitive]
Figure 8-147. CLKSEL_GFX_FCLK Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL_GFX_FCLK CLKDIV_SEL_GFX_F
CLK
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-156. CLKSEL_GFX_FCLK Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 CLKSEL_GFX_FCLK R/W 0h
Selects the clock on gfx fclk [warm reset insensitive]
0x0 = SEL0 : SGX FCLK is from CORE PLL (same as L3 clock)
0x1 = SEL1 : SGX FCLK is from PER PLL (192 MHz clock)
0 CLKDIV_SEL_GFX_FCLK R/W 0h
Selects the divider value on gfx fclk [warm reset insensitive]
0x0 = DIV1 : SGX FCLK is same as L3 Clock or 192MHz Clock
0x1 = DIV2 : SGX FCLK is L3 clock/2 or 192Mhz/2
684
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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