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7.3.6.1 DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
The DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-129. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
31 16
Reserved
R-0
15 10 9 0
Reserved CMD_SLAVE_RATIO
R-0 W-80h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-150. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-10 Reserved Reserved
9-0 CMD_SLAVE_RATIO 0-80h Ratio value for address/command launch timing in DDR PHY macro. This is the fraction of a
clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other
words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to
get the delay value for the slave delay line.
7.3.6.2 DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
The DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) is shown in the figure and table below.
Figure 7-130. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
31 16
Reserved
R-0
15 4 3 0
Reserved DLL_LOCK_DIFF
R-0 W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-151. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
Bit Field Value Description
31-4 Reserved Reserved
3-0 DLL_LOCK_DIFF 0-4h The max number of delay line taps variation allowed while maintaining the master DLL lock.This is
calculated as total jitter/ delay line tap size, where total jitter is half of (incoming clock jitter (pp) +
delay line jitter (pp)).
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SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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