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Table 7-149. Memory-Mapped Registers for DDR2/3/mDDR PHY (continued)
Register Name Type Register Register Address
DATA0_REG_PHY_DQ_OFFSET_0 W Offset value from 0x40 0x11C
DQS to DQ for Data
Macro 0
DATA0_REG_PHY_WR_DATA_SLAVE_RATI W DDR PHY Data Macro 0x04010040 0x120
O_0 0 Write Data Slave
Ratio Register
DATA0_REG_PHY_USE_RANK0_DELAYS W DDR PHY Data Macro 0x0 0x134
0 Delay Selection
Register
DATA0_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Data Macro 0x4 0x138
0 DLL Lock Difference
Register
DATA1_REG_PHY_RD_DQS_SLAVE_RATIO W DDR PHY Data Macro 0x04010040 0x16C
_0 1 Read DQS Slave
Ratio Register
DATA1_REG_PHY_WR_DQS_SLAVE_RATI W DDR PHY Data Macro 0x0 0x180
O_0 1 Write DQS Slave
Ratio Register
DATA1_REG_PHY_WRLVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x194
1 Write Leveling Init
Ratio Register
DATA1_REG_PHY_WRLVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x19C
1 Write Leveling Init
Mode Ratio Selection
Register
DATA1_REG_PHY_GATELVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x1A0
1 DQS Gate Training
Init Ratio Register
DATA1_REG_PHY_GATELVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x1A8
1 DQS Gate Training
Init Mode Ratio
Selection Register
DATA1_REG_PHY_FIFO_WE_SLAVE_RATI W DDR PHY Data Macro 0x0 0x1AC
O_0 1 DQS Gate Slave
Ratio Register
DATA1_REG_PHY_DQ_OFFSET_1 W Offset value from 0x40 0x1C0
DQS to DQ for Data
Macro 1
DATA1_REG_PHY_WR_DATA_SLAVE_RATI W DDR PHY Data Macro 0x04010040 0x1C4
O_0 1 Write Data Slave
Ratio Register
DATA1_REG_PHY_USE_RANK0_DELAYS W DDR PHY Data Macro 0x0 0x1D8
1 Delay Selection
Register
DATA1_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Data Macro 0x4 0x1DC
1 DLL Lock Difference
Register
468
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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