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EMIF
7.3.5.22 PERF_CNT_TIM Register (offset = 90h) [reset = 0h]
PERF_CNT_TIM is shown in Figure 7-112 and described in Table 7-132.
Figure 7-112. PERF_CNT_TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_total_time
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-132. PERF_CNT_TIM Register Field Descriptions
Bit Field Type Reset Description
31-0 reg_total_time R 0h 32-bit counter that continuously counts number for m_clk cycles
elapsed after EMIF is brought out of reset.
447
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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