GPIO Registers
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25.4.1.6 GPIO_IRQSTATUS_0 Register (offset = 2Ch) [reset = 0h]
GPIO_IRQSTATUS_0 is shown in Figure 25-12 and described in Table 25-11.
The GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling, showing all
active events which have been enabled. The fields are read-write. Writing a 1 to a bit clears the bit to 0,
that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled,
active events trigger an actual interrupt request on the IRQ output line.
Figure 25-12. GPIO_IRQSTATUS_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTLINE[n]
R/W1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-11. GPIO_IRQSTATUS_0 Register Field Descriptions
Bit Field Type Reset Description
31-0 INTLINE[n] R/W1C 0h
Interrupt n status.
0x0(W) = No effect.
0x0(R) = IRQ is not triggered.
0x1(W) = Clears the IRQ.
0x1(R) = IRQ is triggered.
4074
General-Purpose Input/Output SPRUH73H–October 2011–Revised April 2013
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