Ethernet Subsystem Registers
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14.5.2.23 TX_INTMASK_CLEAR Register (offset = 8Ch) [reset = 0h]
TX_INTMASK_CLEAR is shown in Figure 14-51 and described in Table 14-62.
CPDMA_INT TX INTERRUPT MASK CLEAR REGISTER
Figure 14-51. TX_INTMASK_CLEAR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
TX7_MASK TX6_MASK TX5_MASK TX4_MASK TX3_MASK TX2_MASK TX1_MASK TX0_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-62. TX_INTMASK_CLEAR Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7 TX7_MASK R/W 0h
TX Channel 7 Mask - Write one to disable interrupt.
6 TX6_MASK R/W 0h
TX Channel 6 Mask - Write one to disable interrupt.
5 TX5_MASK R/W 0h
TX Channel 5 Mask - Write one to disable interrupt.
4 TX4_MASK R/W 0h
TX Channel 4 Mask - Write one to disable interrupt.
3 TX3_MASK R/W 0h
TX Channel 3 Mask - Write one to disable interrupt.
2 TX2_MASK R/W 0h
TX Channel 2 Mask - Write one to disable interrupt.
1 TX1_MASK R/W 0h
TX Channel 1 Mask - Write one to disable interrupt.
0 TX0_MASK R/W 0h
TX Channel 0 Mask - Write one to disable interrupt.
1282
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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