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GPMC
7.1.5.18 GPMC_NAND_COMMAND_i
This register is not a true register, just an address location.
Figure 7-68. GPMC_NAND_COMMAND_i
31 0
GPMC_NAND_COMMAND_i
W-0
LEGEND: W = Write only; -n = value after reset
Table 7-72. GPMC_NAND_COMMAND_i Field Descriptions
Bit Field Value Description
31-0 GPMC_NAND_COMMAND_i 0-FFFF FFFFh Writing data at the GPMC_NAND_COMMAND_i location places the data
as the NAND command value on the bus, using a regular asynchronous
write access.
7.1.5.19 GPMC_NAND_ADDRESS_i
This register is not a true register, just an address location.
Figure 7-69. GPMC_NAND_ADDRESS_i
31 0
GPMC_NAND_ADDRESS_i
W-0
LEGEND: W = Write only; -n = value after reset
Table 7-73. GPMC_NAND_ADDRESS_i Field Descriptions
Bit Field Value Description
31-0 GPMC_NAND_ADDRESS_i 0-FFFF FFFFh Writing data at the GPMC_NAND_ADDRESS_i location places the data
as the NAND partial address value on the bus, using a regular
asynchronous write access.
7.1.5.20 GPMC_NAND_DATA_i
This register is not a true register, just an address location.
Figure 7-70. GPMC_NAND_DATA_i
31 0
GPMC_NAND_DATA_i
R/W
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 7-74. GPMC_NAND_DATA_i Field Descriptions
Bit Field Value Description
31-0 GPMC_NAND_DATA_i 0-FFFF FFFFh Reading data from the GPMC_NAND_DATA_i location or from any
location in the associated chip-select memory region activates an
asynchronous read access.
385
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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